The following is a simplified block diagram of the palmtop IC chip.
Hornet Pin Out
PIN # TYPE SUPPLY DESCRIPTION
==========================================================================================
Power Supply:
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VCC 5 I - Power Supply: 0 to 5.5 Volts
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VDD 5 P - Power Supply: 3.0 to 5.5 Volts
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VDDP 6 P - Pad Power Supply: 3.0 to 5.5 Volts
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GND 10 I - Ground: 0 Volts
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AVDD 1 I - Analog Power Supply: 3.0 to 5.5 Volts
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System RAM Interface:
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AD[0:15] 16 I/O VDD Multiplexed address/data lines, data lines for RAM.
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CA[0:11] 12 O VDD Row/Column Address lines for RAM
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NWE 1 O VDD Write Enable; active low
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NRAS[0:3] 4 I/O VDD RAS outputs to support 4 RAMs; active low
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NUCAS 1 O VDD Upper byte CAS output; active low
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NLCAS 1 O VDD Lower byte CAS output; active low
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Note: The RAM NOE pin is tied to GND.
Card/ROM Interface:
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MD[0:7] 8 I/O VCC 5-Volt data lines
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MA[0:25] 26 O VCC 5-Volt address
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NCWE 1 O VCC Card Write enable; active low
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NRCE 1 O VCC ROM chip enable; active low
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NCS[0:1] 2 O VCC Active low card selects for 2 cards (Byte
access allows card -CE2 to be tied high.)
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NOE 1 O VCC Output enable; active low.
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NCWAIT[0:1] 2 I VCC Card Wait signal used to extend
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bus cycle; active low
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NTKO 1 I VCC Take Over; If NTKO is shorted to ground by a plug-in
card, all system ROM accesses (NRCE) will be
redirected to NCS[0].
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LCD Module Interface:
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YD (FRM) 1 I/O VDD Data for row driver
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LOAD (CL1) 1 O VDD Parallel load pulse
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DF (FI) 1 O VDD Frame inversion signal
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CP (CL2) 1 O VDD Clock pulse; Data is shifted on the
fall of this signal.
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DD[0:7] 8 O VDD Data to display column drivers
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Keyboard:
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KB[0:21] 22 I/O VDD Keyboard I/O
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KBI[22:23] 2 I VDD Dedicated keyboard input
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ON 1 I VDD ON key input
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Serial Port:
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RX 1 I VDD Serial in
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TX 1 O VDD Serial out
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NRI 1 I VDD Ring Indicator
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NCTS 1 I VDD Clear To Send
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NDSR 1 I VDD Data Set Ready
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NDCD 1 I VDD Data Carrier Detect
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NDTR 1 O VDD Data Terminal Ready
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NRTS 1 O VDD Request To Send
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Power Supply Interface:
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VDDOK 1 I VDD Vdd OK input from external power supply
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VCCOK 1 I VCC Vcc OK input from external power supply
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BUP 1 O VDD Backup; driven high to select backup mode
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SON 1 O VDD System on; driven high in run and light sleep
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ADC[0:2] 3 I AVDD A/D inputs (main batteries, backup battery, and
reference) The analog input range is from
1.57V to VDD.
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Emulation/Test:
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NTEST 1 I VDD Test mode input; pulled low to force the part into
test mode
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XCPU 1 I VDD External CPU mode input (disables internal CPU and
reconfigures the GPIO pads for an external CPU
interface)
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Other:
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GPIO[0:7] 8 I/O VDD General Purpose I/O pins: These signals are used to
interface to software controlled functions in the
PCMCIA card port, the display module, and the power
supply. They can be individually configured as input,
output, or as control output signals such as IOR or
IOW. In XCPU mode, these pins provide the interface
for the external CPU.
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GPIO[8:26] 19 I/O VCC
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SPK[0] 1 O VCC Differential speaker driver pin
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SPK[1] 1 O VDD Differential speaker driver pin
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CCV 1 I/O VDD Contrast Control voltage; 5-bit D/A output
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IRO 1 O VCC LED output driver
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IRI 1 I VCC Infrared input sensor
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HXI, HXO 2 I/O VDD 21.477272 MHz quartz crystal connections
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LXI, LXO 2 I/O VDD 32.768 KHz quartz crystal connections
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NRES 1 I VDD Reset; active low
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TOTAL: 195 + 13 no connects = 208-pin package
In the palmtop product, the GPIO[0:26] pins are allocated as follows:
GPIO SUPPLY ALIAS TYPE DESCRIPTION
==========================================================================================
0 VDD IRON3 O 3 Volt IR power on; driven high to enable pullup on IRI
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1 VDD DVEN O Display voltage enable; driven high to turn on display
high voltage
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2 VDD reserved O VPPON for second card
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3 VDD VPPON O Programming voltage on; driven high to allow programming
of FLASH
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4 VDD NREFON O Reference voltage on; active low
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5 VDD PON O Serial port on; driven high to turn on power to serial
driver/receiver chip
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6 VDD NBVD1 I Inverted Battery Voltage Detect 1 from card;
interrupt/wakeup capable
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7 VDD NOAC I Indicates that AC adapter is not plugged in; interrupt
capable
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8 VCC NCD1 I Card detect input 1 from card; NMI interrupt
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9 VCC reserved I Card detect input from second card; NMI interrupt
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10 VCC ECHG I/O Enable charge; resistively driven high to enable charging
circuit; will be driven low externally if battery
overvoltage occurs
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11 VCC reserved I Battery Voltage Detect 1 from second card; interrupt
capable
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12 VCC SPKIN I Speaker input and Battery Voltage Detect 2 from card
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13 VCC PSF I Power supply fault; necessary to cause light sleep wakeup;
previously was reserved for speaker input and Battery
Voltage Detect 2 from second card
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14 VCC BATCAL O Clamps heavy load on battery for capacity measurement
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15 VCC IRON5 O 5 Volt IR power on; driven high to turn on power to IR
receiver circuit
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16 VCC FCHG O Fast charge; driven high to turn on fast charging circuit
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17 VCC NREG O Register select to cards
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18 VCC NROV O Reset overvoltage; low true; pulsed low to enable charging
circuit
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19 VCC CRST O Card reset; high true
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20 VCC WP I Write Protect / NIOIS16 input from card
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21 VCC reserved I Write Protect / NIOIS16 input from second card
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22 VCC NIOR O I/O Read command; active low
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23 VCC NIOW O I/O Write command; active low
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24 VCC RDY I Ready input from card; redefined as interrupt request in
IO mode; interrupt capable
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25 VCC NCD2 I Card detect input 2 from card; used as parallel port
interrupt input from ATS I/O board; reserved for ready
input / IO interrupt request from a second card in a
2-card system
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26 VCC NINPACK I Should be ignored for normal operation; used as serial
port interrupt input from ATS I/O board
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When XCPU is driven high, the GPIO[0:23] pins change function to become an external CPU interface.
GPIO SUPPLY ALIAS TYPE DESCRIPTION
==========================================================================================
0:2 VDD IA[0:2] O Index address; used to select external GPIO registers
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3 VDD HOLD O CPU hold request output
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4 VDD HLDA I CPU hold acknowledge input
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5 VDD INT O Interrupt request output
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6 VDD NMI O Non-Maskable interrupt request output
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7 VDD GIRQ2 I Interrupt request line to 8259
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8:10 VCC S[0:2] I Processor status
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11 VCC NBHE I Bus high enable; active low; multiplexed with status
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12 VCC SPKIN1 I Speaker input 1
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13 VCC SPKIN2 I Speaker input 2
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14 VCC READY O READY signal to external 80C186; used to insert
wait states
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15 VCC GNMI I NMI input
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16 VCC NIOCS O Low true IO chip select with programmable configuration
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17 VCC NREG O Register select to cards
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18 VCC CCLK I CPU clock from CLKOUT of external 80C186
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19 VCC PRES O CPU reset
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20:23 VCC AS[16:19] I Multiplexed address/status lines
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24:26 VCC no change - GPIO[21:23] maintain their normal programmable
functionality in XCPU mode.
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