SIGNAL FUNCTIONAL DESCRIPTION
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NRCE This ROM chip select is hard-addressed (non-programmable) into four separate
address ranges within the CPU address space. The first 64 KB of the ROM chip
are addressed at F0000h to FFFFFh. The next 64 KB of the ROM chip are
addressed at A0000h to AFFFFh. The next 16 KB of the ROM chip are addressed
at BC000h to BFFFFh. The next 16 KB of the ROM chip are addressed at B4000h
to B7FFFh. The remaining portion of a ROM that is larger than 160 KB can be
accessed using bank switching as described in a later section.
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NRAS[1:0] These RAM chip selects have a starting address of 00000h within the CPU
address space. The size is programmable to any multiple of 128 KB from 0 KB
to 640 KB. Following a reset, the size defaults to 128 KB for NRAS[0] and
0KB for NRAS[1].
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NRAS[3:2] These RAM chip selects are intended for additional built- in RAM. These
devices can only be accessed through bank switching.
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NCS[1:0] These RAM/ROM chip selects are intended for plug-in memory. These devices
can only be accessed through bank switching.
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ISA Bus ISA Bus cycles occur when no chip selects are active. In this mode, the 20
bits of CPU address are passed to the device address bus along with the
appropriate memory or I/O read/write signals from the GPIO ports.
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Unused upper-order device address lines are driven low during an access. This means that the accesses will be made to the lower portion of devices that are larger than their configured size. The remaining portion can be accessed via bank switching as described in the following section.
If two or more chip select configurations are programmed to overlap at some addresses, the priority is as shown below. In order for NRAS[1] to be generated, the starting address register must be configured (written to) after a system reset.
CHIP SELECT PRIORITY
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NRCE 1
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NRAS[0] 2
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NRAS[1] 3
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