Bank Control Registers
The bank control registers are read/write registers.
Index Name Bits Comments
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-88h D0 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-89h D0 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank D0 enable
[2:0] Bank D0 device select code
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-8Ah D1 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-8Bh D1 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank D1 enable
[2:0] Bank D1 device select code
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-8Ch D2 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-8Dh D2 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank D2 enable
[2:0] Bank D2 device select code
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-8Eh D3 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-8Fh D3 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank D3 enable
[2:0] Bank D3 device select code
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-90h E0 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-91h E0 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank E0 enable
[2:0] Bank E0 device select code
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-92h E1 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-93h E1 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank E1 enable
[2:0] Bank E1 device select code
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-94h E2 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-95h E2 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank E2 enable
[2:0] Bank E2 device select code
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-96h E3 Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-97h E3 Reg1 [7:4] next 4 MSBs of device address (address bits [17:14])
[3] Bank 3 enable
[2:0] Bank E3 device select code
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-98h C Reg0 [7:0] 8 MSBs of device address (address bits [25:18])
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-99h C Reg1 [7:6] next 2 MSBs of device address (address bits [17:16])
[5] unused
[4] Bank C Attribute Memory Select bit
[3] Bank C enable
[2:0] Bank C device select
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