PIN # TYPE DESCRIPTION
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DD[0:7] 8 O Data to the display column drivers
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CP (CL2) 1 O Clock pulse
The falling edge of this signal shifts data on the DD pins into
the column drivers.
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YD (FRM) 1 I/O Y-axis data for row drivers
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LOAD (CL1) 1 O Parallel load pulse
The falling edge of this signal shifts data on the YD pin into the
row drivers. That edge also causes the column drivers to transfer
their shift register contents to the voltage drivers.
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DF (FI) 1 O Frame inversion signal
This signal toggles on the falling edge of every 17th LOAD pulse.
This is used by the row and column drivers to invert the voltages
used and remove DC bias from the pixels.
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CCV 1 I/O Contrast control voltage
This signal is used to control the high voltage power supply,
thereby controlling the display contrast. See "Programming" on
page 15-515 for more information.
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DVEN 1 I/O Display voltage enable
This GPIO pin is used to enable the high voltage power supply.
See "Programming" on page 15-515 and "General Purpose I/O"
on page 15-545 for more details.
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The display module consists of the liquid crystal display, column drivers, row drivers,
and a bias-supply generator.The column drivers form a shift register with one bit for each column of the display. The data on the DD pins is loaded into this shift register 8 bits at a time by the falling edge of the CP signal. After data is clocked into the shift register for all columns, the falling-edge of the LOAD pulse causes that data to define which dots are on in the currently active row.
The row drivers form a shift register with one bit for each line of the display. The data on the YD pin is clocked into the shift register by the falling edge of the LOAD pulse. Only one bit of the shift register should be true at a time. That bit defines the active row.
The bias-supply generator generates the intermediate voltages required by the row and column drivers.