UART
The serial UART block is implemented using a 16450 compatible macro cell. A 1.84 MHz clock will be supplied for operation of this block. The UART is addressed from 3F8h to 3FFh. Serial drive and receive circuits are provided off chip.
The 1.84 MHz UART clock is available in operating and light sleep modes. The UART clock should be disabled to save power when the UART is not in use. This is done by setting the 16450 baud rate divisor to zero.
The UART supports the following data, control and status lines:
- Transmit Data
- Data Terminal Ready
- Request to Send
- Receive Data
- Data Set Ready
- Clear to Send
- Data Carrier Detect
- Ring Indicator